Notes for 8-bit peripheral bus
I'm slowly building some interface cards, that may eventually get used in a homebrew Z80 computer. Here's some design notes for the connections on each card. While I'm building these cards, I want to be able to connect them (at various times) to any one of
- An Atmega128 development board
- An Apple //e (via my "LittleProto II" card)
- My Z80 homebrew (if/when I start building it)
For the Z80 homebrew, I'm intending to use 2x25 cables as a 'back plane', with IDC DB25 connectors spaced along each cable. But DB25 connectors would be a pain to connect to either the Apple 2 or Atmega128 board. The Atmega board uses 10 pin polarised IDC headers, and it's not too hard to use jumber cables to connect the female IDC headers to the LittleProto breadboard.
So I will make all the peripheral cards with 2 x 10pin IDC PORTs - a 'Control' port and a 'Data' port.
| PIN | Wire Colour | Ctrl Port | Data Port |
|---|---|---|---|
| 0 | Brown | /DEVSEL | D0 |
| 1 | Red | /INT | D1 |
| 2 | Orange | /WR | D2 |
| 3 | Yellow | /RD | D3 |
| 4 | Green | A0 | D4 |
| 5 | Blue | A1 | D5 |
| 6 | Purple | A2 | D6 |
| 7 | Grey | A3 | D7 |
| 8 | White | +5V | +5V |
| 9 | Black | GND | GND |
On the Apple 2, there is there only a single RW signal, not seperate /RD and /WR. RW can be connected to /WR, but needs to be inverted to simulate a /RD signal.
To connect these cards to the hombrew Z80, I will need a "peripheral management unit" (PMU) that connects to the 'back plane', and allows connections for up to 16 peripherals using the control and data ports describd above. This PMU will be constructed as follows:
- Peripherals named P0..PF. headers are named DATA_0..DATAF, and CTRL0..CTRL_F
- Initial build of PMU will probably only have connections for 4 peripherals, P0..P3
- For each peripheral, all signals on both DATA and CTRL headers are common, except /DEVSEL
- /DEVSEL will be constructed by combining /IOREQ and A5..A7
For P0..P3, /DEVSEL created with 74LS138 3-8 decoder
| 74LS138 PIN | Connected to |
|---|---|
| G1 (active high) | +5V |
| G2A (active low) | /IOREQ on Z80 bus |
| G2B (active low) | A7 on Z80 bus |
| Input C | A6 on Z80 bus |
| Input B | A5 on Z80 bus |
| Input A | A4 on Z80 bus |
| Y0 | /DEVSEL on CTRL_0 |
| Y1 | /DEVSEL on CTRL_1 |
| Y2 | /DEVSEL on CTRL_2 |
| Y3 | /DEVSEL on CTRL_3 |
| Y4..Y7 | not connected (would become /DEVSEL on P4..P7 if needed) |
If peripherals P8..PF were needed, a second 74LS138 would be used, wired as above except G1 would be connected to A7 on the Z80 bus, and G2B connected direct to ground.
On each peripheral, A0..A3 can either be ignored (meaning the peripheral will respond to anyone of 16 consecutive addresses) or decoded further as desired.